Article Details

Abstract

In FPGA engineering applications, occasional challenging faults that cannot be located using built-in maintenance and testing methods necessitate the creation of an online data acquisition version. Employing traditional methods with debug cables to run such versions alters existing layout and wiring, consumes significant time, and may cause the fault to disappear. This paper introduces a method for rapidly creating a fault localization version using the ECO approach. This method involves routing abnormal signals to test pins without modifying the original project layout and wiring, followed by auxiliary fault location using an oscilloscope. As an efficient and expeditious means of problem localization, this method demonstrates remarkable flexibility in practical engineering application scenarios. It offers advantages over traditional online data acquisition versioning methods, including reduced version runtime and preservation of the original engineering layout and wiring.

Keywords

FPGA; ECO; fault location

References

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About the authors

Zhang Wei (1982-), male, Han ethnicity, from Nanchang, Jiangxi Province, is an expert in wireless and computing system architecture with a master's degree. His research interests include wireless communication, artificial intelligence (AI), and chip design; Wang Hongzhan (1979-), female, Han ethnicity, from Luoyang, Henan, is a wireless and computing system engineer with a master's degree. Her research interests include wireless communication, artificial intelligence (AI), and chip design.