Article Details

Abstract

Digital control circuits constitute one of the components of the radar receiver system. Under the same functional design, in order to reduce the power consumption of the core device FPGA of the digital control circuit within the full temperature range, the design of the digital control circuit is optimized. Comparative designs are conducted for domestic FPGA devices JFM7K325T and JFMK50T4. It can be obtained that the power consumption of JFM7K325T at normal temperature is approximately 2.3 W, and within the full temperature range (-40 to +60 ℃), the power consumption reaches 1.9 to 8 W, and the maximum current required by the core voltage is 2 A. The power consumption of JFMK50T4 at room temperature is only 1.175 W, and the maximum power consumption reaches 2.8 W within the full temperature range. Under the same environmental temperature, the power consumption is decreased by 1/2 to 3/4. The power supply design, thermal design, and spatial design of the chips are significantly reduced, and the cost of a single chip can also be lowered by 2/3.

Keywords

domesticization; FPGA; low power consumption; digital control circuit

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About the authors

Xu Yawei (1991-), female, Han nationality, from Ya'an, Sichuan, engineer, master's degree, research direction: radar control circuit design.