Article Details

Abstract

To address the issues of low fragment reassembly efficiency and high CPU overhead caused by Fibre Channel (FC) sequence interleaving in massive heterogeneous integration networks with concurrent transmissions from multiple source nodes, this study proposes a sequence reassembly acceleration method based on DMA circular queue control. The method revolves around three types of command rings (read, write, and completion commands) and constructs a hardware-software interaction architecture with multi-pointer cyclic scheduling. It combines hardware-based dynamic descriptors to assign a globally unique identifier to heterogeneous data fragments, manage address offsets, and match protocol features. By integrating the efficient caching and scheduling capabilities of circular queues with the CPU-free characteristics of DMA transfers, the method accurately identifies heterogeneous protocol frames at the hardware level, thereby accelerating the reassembly process of heterogeneous sequence fragments. The proposed method effectively solves the bottlenecks of low hardware-software interaction efficiency and high CPU resource occupation, providing low-latency, high-throughput, and lightweight hardware acceleration support for heterogeneous protocol integration.

Keywords

heterogeneous protocol integration; multi-source sequence fragment reassembly; DMA controller; command ring control; dynamic descriptors

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About the authors

Qi Gongxin (1993-), male, Han nationality, from Nanjing, Jiangsu, engineer, master's student, research direction: high-speed bus; Shi Haifeng (1977-), male, Han nationality, from Nanjing, Jiangsu, engineer, master's student, research direction: high-speed bus; Huang Yongmeng (1996-), male, Han ethnicity, from Nanjing, Jiangsu, engineer, master's student, research direction: high-speed bus; He Hanchen (1994-), male, Han ethnicity, born in Nanjing, Jiangsu, engineer, master's student, research direction: high-speed bus.