Research on Intelligent Generation Technology of VSIPL Code Translation Samples for Embedded Signal Processing
(Nanjing Research Institute of Electronic Technology, Nanjing 210039, China)
Abstract
To address the scarcity of MATLAB-VSIPL parallel corpora and the high cost of manual annotation in the field of embedded signal processing, this paper proposes an LLM-driven intelligent generation method for MATLAB-VSIPL code translation samples. By designing structured translation prompt templates that integrate chain-of-thought reasoning with VSIPL domain knowledge, the method guides the model to generate MATLAB function seeds and corresponding VSIPL candidate implementations. Candidate samples then undergo progressive validation through static compilation checking and dynamic consistency testing. For samples failing validation, compilation error messages and test discrepancy feedback are leveraged to guide iterative repair by the model, thereby establishing a closed-loop MATLAB-VSIPL sample production line for generation, validation, and iteration. Finally, a MinHash-based semantic deduplication strategy is employed to eliminate redundant samples. Experimental results show that this method improves the VSIPL code test pass rate from 4% to 55%, significantly enhancing the quality of MATLAB-VSIPL sample generation.
Keywords
Large Language Model; code translation; VSIPL; chain-of-thought; sample generation
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About the authors
Li Weichao (1988-), male, Han ethnicity, from Zhengzhou, Henan Province, China, engineer, doctoral student, research direction: intelligent development of embedded software.