Article Details

Abstract

This study presents a comprehensive review of the hardware implementation methods and side-channel security protection techniques for the FPGA-based SM4 block cipher algorithm. In terms of hardware implementation, it analyzes the implementation method combining finite field multiplicative inverse operation with affine transformation for S-box permutation, as well as the application of a 32-stage inter-round pipeline architecture, multi-channel parallel processing, and a round key fast switching mechanism. In terms of side-channel security protection, it describes the basic principles of simple power analysis and differential power analysis and their potential threats to the SM4 algorithm. For key leakage points such as S-box outputs and round outputs, a hybrid protection strategy of "masking as the main approach and hiding as a supplement" is proposed. This study provides an important reference for the design, implementation, and security deployment of SM4 encryption and decryption algorithms on the FPGA platform.

Keywords

SM4 algorithm; FPGA; pipeline optimization; side-channel security

References

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About the authors

Zhang Zhenao (2000-), male, Han ethnicity, from Anqing, Anhui Province, assistant engineer, master's student, research direction: communication confidentiality.