Article Details

Abstract

This study presents the design and implementation of a high-isolation single-pole five-throw (SP5T) switch chip operating from DC to 8 GHz. Fabricated using a 0.13 μm silicon-on-insulator (SOI) process, the chip achieves high isolation (> 55 dB) and low insertion loss (< 2.2 dB) through a two-stage series-parallel topology. Key innovations include negative-voltage biasing to reduce parasitic effects, transistor stacking for enhanced power handling (input P1dB > 35 dBm, power tolerance > 36 dBm), and flip-chip (FC) packaging to minimize spatial coupling. Experimental results validate the reliability of the design and its compliance with target specifications. This study provides a cost-effective and highly integrated solution for broadband RF switch design in wireless communication systems compared with GaAs-based alternatives.

Keywords

single-pole five-throw (SP5T); Flip-Chip packaging; high isolation; SOI technology; broadband performance

References

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About the authors

Gu Xun (1992-), male, Han ethnicity, from Chengdu, Sichuan, engineer, master's student, research interests include RF and microwave integrated circuit design; Li Shengjun (1992-), male, Han ethnicity, from Langzhong, Sichuan, engineer, master's student, research interests include RF and microwave integrated circuit design; Pang Bo (1993-), male, Han ethnicity, from Qinhuangdao, Hebei, engineer, master's student, research interests include RF and microwave integrated circuit design; Lu Yuxi (1994-), female, Han ethnicity, from Liangping, Chongqing, engineer, master's student, research interests include RF and microwave integrated circuit design; Yang Demeng (1992-), male, Han ethnicity, from Bole, Xinjiang, engineer, master's student, research interests include RF and microwave integrated circuit design; Deng Chun (1987-), male, Han ethnicity, from Shaodong, Hunan, senior engineer, doctoral student, research interests include RF and microwave integrated circuit design.