Article Details

Title · Authors · Abstract · Keywords · DOI · References

Design of an FPGA-based SDIO Interface Test System

ZHANG Jinze, ZHAO Peng, ZHANG Xian

(No.30 Institute of CETC, Chengdu 610041, China)

Section：Electronic Engineering · Vol. 2026, Issue 20 · Pages：12-16,21 · 2096-4706（2026）20-0012-06 · CLC number：TP274.+2 · Document code：A · DOI：10.19850/j.cnki.2096-4706.2026.20.003

Abstract

To address the low efficiency in batch testing of SDIO interface devices, this study designs an FPGA-based multi-channel parallel test system. With a Xilinx XC7K325T FPGA as the core, the system communicates with the host computer through a Gigabit Ethernet interface, integrates a UDP/IP protocol stack to parse network packets, and employs a custom channel protocol to multiplex and distribute multiple data streams. The FPGA logic instantiates multiple SDIO host controllers that support automatic initialization and parameter configuration. Test results indicate that the system features stable communication and strong scalability, and can meet the requirements for efficient testing of SDIO interface devices.

Keywords

SDIO interface; FPGA (field-programmable gate array); parallel testing; test system

References

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About the authors

Zhang Jinze (1996-), male, Han ethnicity, from Yichun, Heilongjiang, engineer, master's student, research interests include FPGA hardware design and development; Zhao Peng (1986-), male, Han ethnicity, from Hongya, Sichuan, senior engineer, bachelor's degree, research interests include automated testing technologies; Zhang Xian (1996-), male, Han ethnicity, from Jingzhou, Hubei, engineer, bachelor's degree, research interests include FPGA hardware design and development.