Article Details

Abstract

With the development of CMOS technology driving the scaling down of transistor dimensions, radiation-induced Triple-Node Upset (TNU) in CMOS circuits have become a critical issue threatening the reliability of memory devices. To mitigate the impact of soft errors on integrated circuits, this paper proposes a low-overhead latch design capable of tolerating Triple-Node Upsets (LCDOCTL). The LCDOCTL latch mainly consists of a storage module and an interception module, and achieves effective TNU tolerance by utilizing inter-cell data feedback. HSPICE simulation results show that, in comparison with existing TNU-tolerant latch designs, the proposed LCDOCTL latch achieves an average saving of 5.1% in area, 70.31% in propagation delay, 44.12% in power consumption and 84.66% in Power-Delay Product (PDP).

Keywords

radiation; soft error; latch; TNU; tolerance

References

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About the authors

Tang Ye (2001-), male, Han ethnicity, from Yancheng, Jiangsu, is currently pursuing a master's degree in fault-tolerant design of latches.