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电子工程22年10期

2 ~ 6 GHz 高谐波抑制低噪声放大器芯片研究与设计
薛源,吴浩洋
(中国电子科技集团公司第十三研究所,河北 石家庄 050051)

摘  要:提出了一种具有高谐波抑制比的低噪声放大器芯片拓扑结构,利用该拓扑结构,设计了一款基于砷化镓 pHEMT单片工艺的宽带低噪声放大器芯片,覆盖频段 2 ~ 6 GHz,相对带宽达到 100%。在片测试结果显示,该芯片在整个频段内的增益典型值为 25 dB,噪声系数 5.5 dB,输出压缩 1 dB 功率为 7 dBm,二次谐波抑制比达到 35 dBc,与常规宽带低噪声放大器芯片相比,二次谐波抑制比提高了约 15 dB。芯片面积 2.6×2.2 mm2。该低噪声放大器芯片可广泛应用于通信系统中,用于信号的接收放大,同时具有良好的谐波抑制能力,有助于提高通信系统的集成度。


关键词:宽带;低噪声放大器;谐波抑制



DOI:10.19850/j.cnki.2096-4706.2022.10.011


中图分类号:TN722                                        文献标识码:A                                     文章编号:2096-4706(2022)10-0046-05


Research and Design of 2 ~ 6 GHz High Harmonic Suppression Low Noise Amplifier Chip

XUE Yuan, WU Haoyang

(The 13th Research Institute of China Electronics Technology Group Corporation, Shijiazhuang 050051, China)

Abstract: In this paper, a low noise amplifier chip topology with high harmonic rejection ratio is proposed. A broadband low noise amplifier chip based on GaAs pHEMT monolithic process is designed by using this topology, which covers the frequency band of 2~6 GHz and the relative bandwidth reaches 100%. The on-chip test results show that the typical gain of the chip in the whole frequency band is 25 dB, the noise figure is 5.5 dB, the output compression power of 1 dB is 7 dBm, and the second harmonic suppression ratio reaches 35 dBc. Compared with the conventional broadband low noise amplifier chip, the second harmonic suppression ratio is increased by about 15 dB. The chip area is 2.6×2.2 mm2. The low noise amplifier chip can be widely used in communication systems for signal’s reception andamplification. At the same time, it has good harmonic suppression ability, which is helpful to improve the integration of communication systems.

Keywords: broadband; low noise amplifier; harmonic suppression


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作者简介:薛源(1990—),男,汉族,山东济宁人,工程师,硕士学位,研究方向:电路设计。